The first step is to elaborate it, just as we do for simulation.
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Then we can use the convert method on the elaborated instance. The conversion to Verilog generates an equivalent Verilog module in file inc.
Similarly, the conversion to VHDL generates a file inc. This package contains a number of convenience functions that make the conversion easier.
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Note also the use of an inout in the interface. As this is only an issue for ports and as the converter output is non-hierarchical, the issue is not very common and has an easy workaround.
For example, suppose we want to design an incrementer with Gray code output. However, as the bin2gray module is combinatorial, the output bits may have transient glitches, which may not be desirable. This will create an additional latency of a clock cycle, which may not be acceptable, but we will ignore that here.
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This optimization occurs when a variable whose type is an enumerated type is sequentially tested against enumeration items in an if-then-else structure. Also, the appropriate synthesis pragmas for efficient synthesis are generated in the Verilog code.
As a further optimization, function enum was enhanced to support alternative encoding schemes elegantly, using an additional parameter encoding.
This parameter only affects the conversion output, not the behavior of the type. The generated Verilog code for case statements is optimized for an efficient implementation according to the encoding. Note that in contrast, a Verilog designer has to make nontrivial code changes to implement a different encoding scheme.
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The following MyHDL example is a ram model that uses a list of signals to model the internal memory. Note how the list of signals mem is mapped to a Verilog memory. The Verilog converter can perform the expansion into a case statement automatically, based on a higher level description.
The ROM access is described in a single line, by indexing into a tuple of integers. The tuple can be described manually, but also by programmatical means.
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Note that a tuple is used instead of a list to stress the read-only character of the memory. The following example illustrates this functionality. During conversion, the appropriate hierarchical names and parameter values will be substituted. For more info about user-defined code, see User-defined code.
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